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1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2009-2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. multiphase pwm regulator for imvp-6.5? mobile cpus and gpus isl62882, isl62882b the isl62882 is a multiphase pwm buck regulator for miroprocessor or graphics processor core power supply. the multiphase buck converter uses in terleaved phases to reduce the total output voltage ripple with ea ch phase carrying a portion of the total load current, providing better system performance, superior thermal management, lower component cost, reduced power dissipation, and smaller implemen tation area. the isl62882 uses two integrated gate drivers to provide a complete solution. the pwm modulator is based on intersil's robust ripple regulator (r 3 ) technology?. compared with traditional modulators, the r 3 ? modulator commands variable switching frequency during load transients, achieving faster tran sient response. with the same modulator, the switching frequency is reduced at light load, increasing the regulator efficiency. the isl62882 can be configured as cpu or graphics vcore controller and is fully compliant with imvp-6.5 ? specifications. it responds to psi# and dprslpvr signals by adding or dropping phase 2, adjusting overcurrent protection threshold accordingly, and entering/exiting diode emulation mode. it reports the regulator output current through the imon pin. it senses the current by using either discrete resistor or in ductor dcr whose variation over temperature can be thermally compensated by a single ntc thermistor. it uses differential remote voltage sensing to accurately regulate the processor die voltage. the unique split lgate function further increases light load efficiency. the adaptive body diode conduction time reduction func tion minimizes the body diode conduction loss in diode emulation mode. user-selectable overshoot reduction function offers an option to aggressively reduce the output capacitors as well as the option to disable it for users concerned about increased system thermal stress. the isl62882 offers the fb2 function to optimize 1-phase performance. the isl62882b has the same functions as the isl62882, but comes in a different package. features ? programmable 1- or 2-phase cpu mode operation or 1-phase gpu mode operation ? precision multiphase core voltage regulation - 0.5% system accuracy over-temperature - enhanced load line accuracy ? microprocessor voltage identification input - 7-bit vid input, 0v to 1.500v in 12.5mv steps - supports vid changes on-the-fly ? supports multiple current sensing methods - lossless inductor dcr current sensing - precision resistor current sensing ? supports psi# and dprslpvr modes ? superior noise immunity and transient response ? current monitor and thermal monitor ? differential remote voltage sensing ? high efficiency across entire load range ? programmable 1- or 2-phase operation ? two integrated gate drivers ? excellent dynamic current balance between phases ? split lgate1 drivers increases light load efficiency ? fb2 function optimizes 1-phase mode performance ? adaptive body diode conduction time reduction ? user-selectable overshoot reduction function ? small footprint 40 ld 5x5 or 48 ld 6x6 tqfn packages ? pb-free (rohs compliant) applications ? notebook core voltage regulator ? notebook gpu voltage regulator june 21, 2011 fn6890.4
isl62882, isl62882b 2 fn6890.4 june 21, 2011 ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # isl62882irtz 62882 irtz -40 to +100 40 ld 5x5 tqfn l40.5x5 ISL62882HRTZ 62882 hrtz -10 to +100 40 ld 5x5 tqfn l40.5x5 isl62882bhrtz 62882 bhrtz -10 to +100 48 ld 6x6 tqfn l48.6x6 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl62882 , isl62882b . for more information on msl please see techbrief tb363 . pin configurations isl62882 (40 ld tqfn) top view isl62882b (48 ld tqfn) top view 1 40 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 gnd pad (bottom) v r _ o n v i d 5 v i d 4 v i d 3 v i d 2 v i d 1 v i d 0 boot2 c l k _ e n # vr_tt# ntc ugate2 phase2 vssp2 vccp lgate1b lgate1a vssp1 comp isen2 fb2 fb vw psi# rbias pgood v i d 6 d p r s l p v r lgate2 phase1 isum- isum+ vin ugate1 boot1 imon vdd vsen rtn isen1 v r_o n vid 5 v id4 vid3 vid 2 v id1 vid0 boot2 c lk_ en# vr_tt# ntc ugate2 phase2 vssp2 vccp lgate1b lgate1a vssp1 comp fb2 fb vw psi# rbias pgood vi d6 dpr slp vr lgate2 phase1 isum- isum+ vin boot1 imon vdd vsen rtn isen1 1 48 2 3 4 5 6 7 8 9 10 36 35 34 33 32 31 30 29 28 27 47 46 45 44 43 42 41 40 39 13 14 15 16 17 18 19 20 21 22 23 24 11 12 38 37 26 25 isen2 gnd nc nc nc nc ugate1 nc n c n c (bottom)
isl62882, isl62882b 3 fn6890.4 june 21, 2011 functional pin descriptions isl62882 isl62882b symbol description - 7 gnd signal common of the ic. unless otherwise stated, signals are referenced to the gnd pin. 1 2 pgood power-good open-drain output indicating when the regulator is able to supply regulated voltage. pull-up externally with a 680 resistor to vccp or 1.9k to 3.3v. 2 3 psi# low load current indicator input. when asserted low, indicates a reduced load current condition. 3 4 rbias a resistor to gnd sets internal current reference. use 147k or 47k . the choice of rbias value, together with the isen2 pin configuration and the external resistance from the comp pin to gnd, programs the controller to enable/disable the overshoot reduction function and to select the cpu/gpu mode. 4 5 vr_tt# thermal overload output indicator. 5 6 ntc thermistor input to vr_tt# circuit. 6 8 vw a resistor from this pin to comp programs the switching frequency (8k gives approximately 300khz). 7 9 comp this pin is the output of the error amplifier. also, a resistor across this pin and gnd adjusts the overcurrent threshold. 8 10 fb this pin is the inverting input of the error amplifier. 9 11 fb2 there is a switch between the fb2 pin and the fb pin. the switch is on in 2-phase mode and is off in 1-phase mode. the components connecting to fb2 are used to adjust the compensation in 1-phase mode to achieve optimum performance. 10 13 isen2 individual current sensing for phase 2. when isen2 is pulled to 5v vdd, the controller will disable phase 2. 11 14 isen1 individual current sensing for phase 1. 12 15 vsen remote core voltage sense input. connect to microprocessor die. 13 16 rtn remote voltage sensing return. conn ect to ground at microprocessor die. 14, 15 17, 18 isum- and isum+ droop current sense input. 16 19 vdd 5v bias power. 17 20 vin battery supply voltage, used for feed-forward. 18 22 imon an analog output. imon outputs a current proportional to the regulator output current. 19 24 boot1 connect an mlcc capacitor across the bo ot1 and the phase1 pins. the boot capacitor is charged through an internal boot diode connecte d from the vccp pin to the boot1 pin, each time the phase1 pin drops below vccp minus the voltage dropped across the internal boot diode. 20 25 ugate1 output of the phase-1 high -side mosfet gate driver. connect the ugate1 pin to the gate of the phase-1 high-side mosfet. 21 26 phase1 current return path for the phase-1 high-sid e mosfet gate driver. connect the phase1 pin to the node consisting of the high-s ide mosfet source, the low-side mosfet drain, and the output inductor of phase-1. 22 27 vssp1 current return path for the phase-1 low-side mosfet gate driver. connect the vssp1 pin to the source of the phase-1 low-side mosfet throug h a low impedance path, preferably in parallel with the traces connecting the lgate1a and th e lgate1b pins to the gates of the phase-1 low-side mosfets. 23 28 lgate1a output of the phase-1 low-side mosfet gate driver that is always active. connect the lgate1a pin to the gate of the phase-1 low-side mosfet that is ac tive all the time. 24 29 lgate1b another output of the phase-1 low-side mosfet gate driver. this gate driver will be pulled low when the dprslpvr pin logic is high. connect the lgate1b pin to the gate of the phase-1 low-side mosfet that is idle in deeper sleep mode. - - lgate1 output of the phase-1 low-side mosfet gate driver. connect the lgate1 pin to the gate of the phase-1 low-side mosfet.
isl62882, isl62882b 4 fn6890.4 june 21, 2011 25 30 vccp input voltage bias for the internal gate drivers. connect +5v to the vccp pin. decouple with at least 1f of an mlcc capacitor to vssp1 and vssp2 pins respectively. 26 32 lgate2 output of the phase-2 low-side mosfet gate driver. connect the lgate2 pin to the gate of the phase-2 low-side mosfet. 27 33 vssp2 current return path for the phase-2 conver ter low-side mosfet gate driver. connect the vssp2 pin to the source of the phase-2 low-side mosf et through a low impedance path, preferably in parallel with the trace connecting the lgate2 pi n to the gate of the phase-2 low-side mosfet. 28 34 phase2 current return path for the phase-2 high-sid e mosfet gate driver. connect the phase2 pin to the node consisting of the high-s ide mosfet source, the low-side mosfet drain, and the output inductor of phase-2. 29 35 ugate2 output of the phase-2 high -side mosfet gate driver. connect the ugate2 pin to the gate of the phase-2 high-side mosfet. 30 36 boot2 connect an mlcc capacitor across the bo ot2 and the phase2 pins. the boot capacitor is charged through an internal boot diode connecte d from the vccp pin to the boot2 pin, each time the phase2 pin drops below vccp minus the voltage dropped across the internal boot diode. 31 thru 37 38 thru 44 vid0 thru vid6 vid input with vid0 = lsb and vid6 = msb. 38 45 vr_on voltage regulator enable input. a high le vel logic signal on this pin enables the regulator. 39 46 dprslpvr deeper sleep enable signal. a high level logi c signal on this pin indica tes that the microprocessor is in deeper sleep mode. 40 47 clk_en# open drain output to enable system pll cloc k. it goes low 13 switching cycles after vcore is within 10% of vboot. -48 ncno connect. pad pad bottom the bottom pad of isl62882b is electr ically connected to the gnd pin inside the ic. functional pin descriptions (continued) isl62882 isl62882b symbol description
isl62882, isl62882b 5 fn6890.4 june 21, 2011 block diagram vid0 vid1 vid2 vid3 vid4 vid5 vid6 vr_on psi# dprslpvr mode control dac and soft- start rtn e/a fb idroop current sense isum+ isum- imon imon comp driver shoot through protection driver pwm control logic driver shoot through protection driver pwm control logic protection pgood clk_en# adj. ocp threshold lgate1a phase1 ugate1 boot1 lgate2 phase2 ugate2 boot2 vsen clock vw isen2 isen1 current balance vin flt woc oc 2.5x vssp1 vssp2 woc oc vccp vin vdac modulator modulator ibal vin vdac ibal vin vdac comp vw comp comp pgood & clk_en# logic gnd vdd vr_tt# ntc 1.20v 1.24v 54a 6a rbias gain select 60a number of phases ibal
isl62882, isl62882b 6 fn6890.4 june 21, 2011 absolute maximum rating s thermal information supply voltage, vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7v battery voltage, vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28v boot voltage (boot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +33v boot to phase voltage (boot-phase) . . . . . . . . . . . . . . . . -0.3v to +7v(dc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +9v(<10ns) phase voltage (phase) . . . . . . . . . . . . . . . . -7v (<20ns pulse width, 10j) ugate voltage (ugate) . . . . . . . . . . . . . . . . . . . . phase-0.3v (dc) to boot . . . . . . . . . . . . . . . . . . . . . p hase-5v (<20ns pulse width, 10j) to boot lgate1a and 1b and lgate2 voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v (dc) to vdd+0.3v lgate1a and 1b . . . . . . . . . . . . . . . . . . . . . . -2.5v (<20ns pulse width, 2.5j) to vdd+0.3v lgate1a and 1b . . . . . . . . . . . . . . . . . . . . . . . . -2.5v (<20ns pulse width, 5j) to vdd+0.3v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to (vdd +0.3v) open drain outputs, pgood, vr_tt#, clk_en# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7v thermal resistance (typical) ja (c/w) jc (c/w) 40 ld tqfn package (notes 4, 5) . . . . . . . 32 3 48 ld tqfn package (notes 4, 5) . . . . . . . 29 2 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c maximum junction temperature (plastic package) . . . . . . . . . . . .+150c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions supply voltage, vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v 5% battery voltage, vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5v to 25v ambient temperature ISL62882HRTZ, isl62882bhrtz . . . . . . . . . . . . . . . . .-10c to +100c isl62882irtz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +100c junction temperature ISL62882HRTZ, isl62882bhrtz . . . . . . . . . . . . . . . . .-10c to +125c isl62882irtz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications operating conditions: vdd = 5v, t a = -40c to +100c, f sw = 300khz, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +100c. parameter symbol test conditions min (note 6) typ max (note 6) units input power supply +5v supply current i vdd vr_on = 3.3v 4 4.6 ma vr_on = 0v 1 a battery supply current i vin vr_on = 0v 1 a v in input resistance r vin vr_on = 3.3v 900 k power-on-reset threshold por r v dd rising 4.35 4.5 v por f v dd falling 4.00 4.15 v system and references system accuracy hrtz %error (v cc_core ) no load; closed loop, active mode range vid = 0.75v to 1.50v, -0.5 +0.5 % vid = 0.5v to 0.7375v -8 +8 mv vid = 0.3v to 0.4875v -15 +15 mv irtz %error (v cc_core ) no load; closed loop, active mode range vid = 0.75v to 1.50v -0.8 +0.8 % vid = 0.5v to 0.7375v -10 +10 mv vid = 0.3v to 0.4875v -18 +18 mv v boot 1.0945 1.100 1.1055 v maximum output voltage v cc_core(max) vid = [0000000] 1.500 v minimum output voltage v cc_core(min) vid = [1100000] 0.300 v r bias voltage r bias = 147k 1.45 1.47 1.49 v
isl62882, isl62882b 7 fn6890.4 june 21, 2011 channel frequency nominal channel frequency f sw(nom) rfset = 7k , 2-channel operation, v comp = 1v 285 300 315 khz adjustment range 200 500 khz amplifiers current-sense amplifier input offset i fb = 0a -0.15 +0.15 mv error amp dc gain a v0 90 db error amp gain-bandwidth product gbw c l = 20pf 18 mhz isen imbalance voltage maximum of isens - minimum of isens 1 mv input bias current 20 na power-good and protection monitors pgood low voltage v ol i pgood = 4ma 0.26 0.4 v pgood leakage current i oh pgood = 3.3v -1 1 a pgood delay tpgd clk_enable# low to pgood high 6.3 7.6 8.9 ms gate driver ugate pull-up resistance r ugpu 200ma source current 1.0 1.5 ugate source current i ugsrc ugate - phase = 2.5v 2.0 a ugate sink resistance r ugpd 250ma sink current 1.0 1.5 ugate sink current i ugsnk ugate - phase = 2.5v 2.0 a lgate1a and 1b pull-up resistance r lgpu 250ma source current 2.0 3 lgate1a and 1b source current i lgsrc lgate1a and 1b - vssp1 = 2.5v 1.0 a lgate1a and 1b sink resistance r lgpd 250ma sink current 1 1.8 lgate1a and 1b sink current i lgsnk lgate1a and 1b - vssp1 = 2.5v 2.0 a ugate1 to lgate1a and 1b deadtime t ugflgr ugate1 falling to lgate1a and 1b rising, no load 23 ns lgate1a and 1b to ugate1 deadtime t lgfugr lgate1a and 1b falling to ugate1 rising, no load 28 ns lgate pull-up resistance r lgpu 250ma source current 1.0 1.5 lgate source current i lgsrc lgate - vssp = 2.5v 2.0 a lgate sink resistance r lgpd 250ma sink current 0.5 0.9 lgate sink current i lgsnk lgate - vssp = 2.5v 4.0 a ugate to lgate deadtime t ugflgr ugate falling to lgate rising, no load 23 ns lgate to ugate deadtime t lgfugr lgate falling to ugate rising, no load 28 ns bootstrap diode forward voltage v f pvcc = 5v, i f = 2ma 0.58 v reverse leakage i r v r = 25v 0.2 a protection overvoltage threshold ov h vsen rising above setpoint for >1ms 150 195 240 mv severe overvoltage threshold ov hs vsen rising for >2s 1.525 1.55 1.575 v oc threshold offset at rcomp = open circuit 2-phase configuration, isum- pin current 18.3 20.2 22.1 a 1-phase configuration, isum- pin current 8.2 10.1 12.0 a current imbalance threshold one isen above another isen for >1.2ms 9 mv undervoltage threshold uv f vsen falling below setpoint for >1.2ms -355 -295 -235 mv electrical specifications operating conditions: vdd = 5v, t a = -40c to +100c, f sw = 300khz, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +100c. (continued) parameter symbol test conditions min (note 6) typ max (note 6) units
isl62882, isl62882b 8 fn6890.4 june 21, 2011 logic thresholds vr_on input low v il(1.0v) 0.3 v vr_on input high v ih(1.0v) ISL62882HRTZ 0.7 v v ih(1.0v) isl62882irtz 0.75 v vid0-vid6, psi#, and dprslpvr input low v il(1.0v) 0.3 v vid0-vid6, psi#, and dprslpvr input high v ih(1.0v) 0.7 v thermal monitor ntc source current ntc = 1.3v 53 60 67 a over-temperature threshold v (ntc) falling 1.18 1.2 1.22 v vr_tt# low output resistance r tt i = 20ma 6.5 9 clk_en# output levels clk_en# low output voltage v ol i = 4ma 0.26 0.4 v clk_en# leakage current i oh clk_en# = 3.3v -1 1 a current monitor imon output current i imon isum- pin current = 20a 108 120 132 a isum- pin current = 10a 51 60 69 a isum- pin current = 5a 22 30 37.5 a imon clamp voltage v imonclamp 1.1 1.15 v current sinking capability 275 a inputs vr_on leakage current i vr_on vr_on = 0v -1 0a vr_on = 1v 0 1 a vidx leakage current i vidx vidx = 0v -1 0a vidx = 1v 0.45 1 a psi# leakage current i psi# psi# = 0v -1 0a psi# = 1v 0.45 1 a dprslpvr leakage current i dprslpvr dprslpvr = 0v -1 0a dprslpvr = 1v 0.45 1 a slew rate slew rate (for vid change) sr 56.5 mv/s notes: 6. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established by characterization and are not production tested. electrical specifications operating conditions: vdd = 5v, t a = -40c to +100c, f sw = 300khz, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +100c. (continued) parameter symbol test conditions min (note 6) typ max (note 6) units
isl62882, isl62882b 9 fn6890.4 june 21, 2011 gate driver timing diagram pwm ugate lgate 1v 1v t ugflgr t rl t fu t ru t fl t lgfugr
isl62882, isl62882b 10 fn6890.4 june 21, 2011 simplified application circuits figure 1. typical cpu application circuit using dcr sensing l2 l1 v o phase2 ugate2 rs2 rs1 cs1 rsum2 rsum1 rn cn ri boot2 (bottom pad) vss vin lgate2 isen2 phase1 ugate1 boot1 lgate1a isen1 isum+ isum- fb vsen comp rdroop rfset vw rtn pgood vr_on dprslpvr psi# vids rbias ntc clk_en# v+5 vin vin vdd imon clk_en# vid<0:6> psi# dprslpvr vr_on pgood rimon vsssense vccsense imon vr_tt# vr_tt# v+5 vccp vssp2 vssp1 o c isl62882 rbias rntc o c ris cis lgate1b fb2 cs2 figure 2. typical cpu application circuit using resistor sensing l2 l1 phase2 ugate2 rs2 rs1 cs1 rsum2 rsum1 cn ri boot2 (bottom pad) vss vin lgate2 isen2 phase1 ugate1 boot1 lgate1a isen1 isum+ isum- fb vsen comp rdroop rfset vw rtn pgood vr_on dprslpvr psi# vids rbias ntc clk_en# v+5 vin vin vdd imon clk_enable # vid<0:6> psi# dprslpvr vr_on imvp6_pwrgd rimon vsssense vccsense imon vr_tt# vr_tt# v+5 vccp vssp2 vssp1 isl62882 rbias rntc o c ris cis lgate1b fb2 cs2 v o rsen2 rsen1
isl62882, isl62882b 11 fn6890.4 june 21, 2011 figure 3. typical gpu applicat ion circuit using dcr sensing l v o phase2 ugate2 rsum rn cn ri boot2 (bottom pad) vss vin lgate2 isen2 phase1 ugate1 boot1 lgate1a isen1 isum+ isum- fb vsen comp rdroop rfset vw rtn pgood vr_on dprslpvr psi# vids rbias ntc clk_en# v+5 vin vin vdd imon clk_en# vid<0:6> psi# dprslpvr vr_on pgood rimon vsssense vccsense imon vr_tt# vr_tt# v+5 vccp vssp2 vssp1 o c isl62882 rbias rntc o c ris cis lgate1b fb2 figure 4. typical gpu application circuit using resistor sensing l phase2 ugate2 rsum2 cn ri boot2 (bottom pad) vss vin lgate2 isen2 phase1 ugate1 boot1 lgate1a isen1 isum+ isum- fb vsen comp rdroop rfset vw rtn pgood vr_on dprslpvr psi# vids rbias ntc clk_en# v+5 vin vin vdd imon clk_enable # vid<0:6> psi# dprslpvr vr_on imvp6_pwrgd rimon vsssense vccsense imon vr_tt# vr_tt# v+5 vccp vssp2 vssp1 isl62882 rbias rntc o c ris cis lgate1b fb2 v o rsen
isl62882, isl62882b 12 fn6890.4 june 21, 2011 theory of operation multiphase r 3 ? modulator the isl62882 is a multiphase regulator implementing intel ? imvp-6.5? protocol. it can be programmed for 1- or 2-phase operation for microprocessor core applications. it uses intersil patented r 3 ? (robust ripple regulator?) modulator. the r 3 ? modulator combines the best fe atures of fixed frequency pwm and hysteretic pwm while eliminat ing many of their shortcomings. figure 5 conceptually shows the isl62882 multiphase r 3 ? modulator circuit, and figure 6 shows the operation principles. a current source flows from the vw pin to the comp pin, creating a voltage window set by the resistor between the two pins. this voltage window is called vw window in the following discussion. inside the ic, the modulator uses the master clock circuit to generate the clocks for the slave circuits. the modulator discharges the ripple capacitor c rm with a current source equal to g m v o , where g m is a gain factor. c rm voltage v crm is a sawtooth waveform traversing between the vw and comp voltages. it resets to vw when it hits comp, and generates a one-shot master clock signal. a phase sequencer distributes the master clock signal to the slave circuits. if the isl62882 is in 2-phase mode, the master clock signal will be distributed to phases 1 and 2, and the clock1 and clock2 signals will be 180 out-of-phase. if the isl62882 is in 1-phase mode, the master clock signal will be distributed to phases 1 only and be the clock1 signal. each slave circuit has its own ripple capacitor c rs , whose voltage mimics the inductor ripple current. a g m amplifier converts the inductor voltage into a current source to charge and discharge c rs . the slave circuit turns on its pwm pulse upon receiving the clock signal, and the current source charges c rs . when c rs voltage v crs hits vw, the slave circuit turns off the pwm pulse, and the current source discharges c rs . figure 5. r 3 ? modulator circuit crm gmvo master clock vw comp master clock phase sequencer clock1 r i l1 gm clock1 phase1 crs1 vw s q pwm1 l1 r i l2 gm clock2 phase2 crs2 vw s q pwm2 l2 co vo vcrm vcrs1 vcrs2 master clock circuit slave circuit 1 slave circuit 2 clock2 vw figure 6. r 3 ? modulator operation principles in steady state comp vcrm master clock pwm1 vw clock1 pwm2 clock2 hysteretic window vcrs2 vcrs1 vw comp vcrm master clock pwm1 vcrs1 vw clock1 pwm2 vcrs2 clock2 vw figure 7. r 3 ? modulator operation principles in load insertion response
isl62882, isl62882b 13 fn6890.4 june 21, 2011 since the isl62882 works with v crs , which are large amplitude and noise-free synthe sized signals, the isl62882 achieves lower phase jitter than conventional hysteretic mode and fixed pwm mode controllers. unlike conventional hysteretic mode converters, the isl62882 has an er ror amplifier that allows the controller to maintain a 0.5% output voltage accuracy. figure 7 shows the operation principles during load insertion response. the comp voltage rises during load insertion, generating the master clock signal more quickly, so the pwm pulses turn on earlier, increasing the effective switching frequency, which allows for higher control lo op bandwidth than conventional fixed frequency pwm controllers. the vw voltage rises as the comp voltage rises, making the pwm pulses wider. during load release response, the comp voltage falls. it takes the master clock circuit longer to generate the next master clock signal so the pwm pulse is held off until needed. the vw voltage falls as the vw voltage falls, reducing the current pwm pulse width. this kind of behavior gives the isl62882 excellent response speed. the fact that both phases share the same vw window voltage also ensures excellent dynamic current balance between phases. diode emulation and period stretching isl62882 can operate in diode emulation (de) mode to improve light load efficiency. in de mode, the low-side mosfet conducts when the current is flowing from source to drain and does not allow reverse current, emulating a diode. as figure 8 shows, when lgate is on, the low-side mosfet carries current, creating negative voltage on the phase node due to the voltage drop across the on-resistance. the isl62882 monitors the current through monitoring the phase node voltage. it turns off lgate when the phase node voltage reaches zero to prevent the inductor current from reversin g the direction and creating unnecessary power loss. if the load current is light enough, as figure 8 shows, the inductor current will reach and stay at ze ro before the next phase node pulse, and the regulator is in discontinuous conduction mode (dcm). if the load current is heavy enough, the inductor current will never reach 0a, and the regulator is in ccm although the controller is in de mode. figure 9 shows the operation principle in diode emulation mode at light load. the load gets incremen tally lighter in the three cases from top to bottom. the pwm on-time is determined by the vw window size, therefore is the same, making the inductor current triangle the same in the three cases. the isl62882 clamps the ripple capacitor voltage v crs in de mode to make it mimic the inductor current. it takes the comp voltage longer to hit v crs , naturally stretching the switching period. the inductor current triangles move further apart from each other such that the inductor current average value is equal to the load current. the reduced switching frequency helps to increase light load efficiency. start-up timing with the controller's v dd voltage above the por threshold, the start-up sequence begins when vr _on exceeds the 3.3v logic high threshold. figure 10 shows the typical start-up timing when the isl62882 is configured for cpu vr application. the isl62 882 uses digital soft-start to ramp-up da c to the boot voltage of 1.1v at about 2.5mv/s. once the output voltage is within 10% of the boot voltage for 13 pwm cycles (43s for frequency = 300khz), clk_en# is pulled low and dac slews at 5mv/s to the voltage set by the vid pins. pgood is asserted high in approximately 7ms. similar results occur if vr_on is tied to v dd , with the soft-start sequence starting 120s after v dd crosses the por threshold. figure 11 shows the typical start- up timing when the isl62882 is configured for gpu vr application. the isl62882 uses digital soft start to ramp up dac to the voltage set by the vid pins. the slew rate is 5mv/s when there is dprslpvr = 0, and is doubled when there is dprslpvr = 1. once the output voltage is within 10% of the target voltage for 13 pwm cycles (43s for frequency = 300khz), clk_en# is pulled low. pgood is asserted high in approximately 7ms. similar results occur if vr_on is tied to v dd , with the soft-start sequence starting 120s after v dd crosses the por threshold. ugate phase il lgate figure 8. diode emulation il il vcrs il vcrs vcrs vw ccm/dcm boundary light dcm deep dcm vw vw figure 9. period stretching
isl62882, isl62882b 14 fn6890.4 june 21, 2011 voltage regulation and load line implementation after the start sequence, the isl62882 regulates the output voltage to the value set by th e vid inputs per table 1. the isl62882 will control the no-load output voltage to an accuracy of 0.5% over the range of 0.75v to 1.5v. a differential amplifier allows voltage sensing for precise voltage regulation at the microprocessor die. table 1. vid table vid6 vid5 vid4 vi d3 vid2 vid1 vid0 v o (v) 0 0 0 0 0 0 0 1.5000 00000011.4875 00000101.4750 0 0 0 0 0 1 1 1.4625 0 0 0 0 1 0 0 1.4500 00001011.4375 0 0 0 0 1 1 0 1.4250 00001111.4125 0 0 0 1 0 0 0 1.4000 00010011.3875 00010101.3750 0 0 0 1 0 1 1 1.3625 vdd vr_on dac 800s 2.5mv/s vboot 5mv/s vid command voltage 90% 13 switching cycles clk_en# pgood ~7ms figure 10. soft-start waveforms for cpu vr application vdd vr_on dac 120s slew rate vid command voltage 90% 13 switching cycles clk_en# pgood ~7ms figure 11. soft-start waveforms for gpu vr application 0 0 0 1 1 0 0 1.3500 00011011.3375 0 0 0 1 1 1 0 1.3250 00011111.3125 0 0 1 0 0 0 0 1.3000 00100011.2875 00100101.2750 0 0 1 0 0 1 1 1.2625 0 0 1 0 1 0 0 1.2500 00101011.2375 0 0 1 0 1 1 0 1.2250 00101111.2125 0 0 1 1 0 0 0 1.2000 00110011.1875 00110101.1750 00110111.1625 0 0 1 1 1 0 0 1.1500 00111011.1375 00111101.1250 00111111.1125 01000001.1000 01000011.0875 01000101.0750 0 1 0 0 0 1 1 1.0625 0 1 0 0 1 0 0 1.0500 01001011.0375 0 1 0 0 1 1 0 1.0250 01001111.0125 0 1 0 1 0 0 0 1.0000 01010010.9875 01010100.9750 0 1 0 1 0 1 1 0.9625 0 1 0 1 1 0 0 0.9500 01011010.9375 0 1 0 1 1 1 0 0.9250 01011110.9125 0 1 1 0 0 0 0 0.9000 01100010.8875 01100100.8750 table 1. vid table (continued) vid6 vid5 vid4 vid3 vid2 vid1 vid0 v o (v)
isl62882, isl62882b 15 fn6890.4 june 21, 2011 01100110.8625 01101000.8500 01101010.8375 01101100.8250 01101110.8125 01110000.8000 01110010.7875 01110100.7750 01110110.7625 01111000.7500 01111010.7375 01111100.7250 01111110.7125 10000000.7000 10000010.6875 10000100.6750 10000110.6625 10001000.6500 10001010.6375 10001100.6250 10001110.6125 10010000.6000 10010010.5875 10010100.5750 10010110.5625 10011000.5500 10011010.5375 10011100.5250 10011110.5125 10100000.5000 10100010.4875 10100100.4750 10100110.4625 10101000.4500 10101010.4375 10101100.4250 10101110.4125 10110000.4000 10110010.3875 table 1. vid table (continued) vid6 vid5 vid4 vi d3 vid2 vid1 vid0 v o (v) 10110100.3750 1 0 1 1 0 1 1 0.3625 1 0 1 1 1 0 0 0.3500 10111010.3375 1 0 1 1 1 1 0 0.3250 10111110.3125 1 1 0 0 0 0 0 0.3000 11000010.2875 11000100.2750 1 1 0 0 0 1 1 0.2625 1 1 0 0 1 0 0 0.2500 11001010.2375 1 1 0 0 1 1 0 0.2250 11001110.2125 1 1 0 1 0 0 0 0.2000 11010010.1875 11010100.1750 11010110.1625 11011000.1500 11011010.1375 11011100.1250 11011110.1125 11100000.1000 11100010.0875 11100100.0750 1 1 1 0 0 1 1 0.0625 1 1 1 0 1 0 0 0.0500 11101010.0375 1 1 1 0 1 1 0 0.0250 11101110.0125 1 1 1 1 0 0 0 0.0000 1 1 1 1 0 0 1 0.0000 1 1 1 1 0 1 0 0.0000 1 1 1 1 0 1 1 0.0000 1 1 1 1 1 0 0 0.0000 1 1 1 1 1 0 1 0.0000 1 1 1 1 1 1 0 0.0000 1 1 1 1 1 1 1 0.0000 table 1. vid table (continued) vid6 vid5 vid4 vid3 vid2 vid1 vid0 v o (v)
isl62882, isl62882b 16 fn6890.4 june 21, 2011 as the load current increases from zero, the output voltage will droop from the vid table value by an amount proportional to the load current to achieve the load line. the isl62882 can sense the inductor current through the in trinsic dc resistance (dcr) of the inductors as shown in figure 1 or through resistors in series with the inductors as shown in figure 2. in both methods, capacitor c n voltage represents the inductor total currents. a droop amplifier converts c n voltage into an internal current source with the gain set by resistor r i . the current source is used for load line implementation, current monitor and overcurrent protection. figure 12 shows the load line implementation. the isl62882 drives a current source i droop out of the fb pin, described by equation 1. when using inductor dcr current sensing, a single ntc element is used to compensate the positive temperature coefficient of the copper winding thus sustaining the load line accuracy with reduced cost. i droop flows through resistor r droop and creates a voltage drop as shown in equation 2. v droop is the droop voltage required to implement load line. changing r droop or scaling i droop can both change the load line slope. since i droop also sets the overcurrent protection level, it is recommended to first scale i droop based on ocp requirement, then select an appropriate r droop value to obtain the desired load line slope. differential sensing figure 12 also shows the differential voltage sensing scheme. vcc sense and vss sense are the remote voltage sensing signals from the processor die. a unity ga in differential amplifier senses the vss sense voltage and add it to the dac output. the error amplifier regulates the invertin g and the non-inverting input voltages to be equal as shown in equation 3: rewriting equation 3 and substi tution of equation 2 gives: equation 4 is the exact equati on required for load line implementation. the vcc sense and vss sense signals come from the processor die. the feedback will be open circuit in the absence of the processor. as figure 12 shows, it is recommended to add a ?catch? resistor to feed the vr local output voltage back to the compensator, and add another ?catch? resistor to connect the vr local output ground to the rtn pin. these resistors, typically 10 ~100 , will provide voltage feedback if the system is powered up without a processor installed. phase current balancing the isl62882 monitors individu al phase average current by monitoring the isen1 and isen2 voltages. figure 13 shows the current balancing circuit recommended for isl62882. each phase node voltage is averaged by a low-pass filter consisting of r s and c s , and presented to the corresponding isen pin. r s should be routed to inductor phase-node pad in order to eliminate the effect of phase no de parasitic pcb dcr. equations 5 and 6 give the isen pin voltages: where r dcr1 and r dcr2 are inductor dcr; r pcb1 and r pcb2 are parasitic pcb dcr between the inductor output side pad and the output voltage rail; and i l1 and i l2 are inductor average currents. the isl62882 will adjust the phase pulse-width relative to the other phase to make v isen1 = v isen2 , thus to achieve i l1 = i l2 , when there are r dcr1 = r dcr2 and r pcb1 = r pcb2 . using same components for l1 and l2 will provide a good match of r dcr1 and r dcr2 . board layout will determine r pcb1 and r pcb2 . it is recommended to have symmetrical layout for the power delivery path between each inductor and the output voltage rail, such that r pcb1 = r pcb2 . figure 12. differential sensing and load line implementation x 1 e/a dac vid<0:6> rdroop idroop vdac vdroop fb comp vcc sense vss sense vids rtn vss internal to ic ?catch? resistor ?catch? resistor vr local vo i droop 2xv cn r i ---------------- = (eq. 1) v droop r droop i droop = (eq. 2) vcc sense v + droop v dac vss sense + = (eq. 3) vcc sense vss sense ? v dac r droop i droop ? = (eq. 4) internal to ic v o isen2 rs cs isen1 rs cs l2 l1 rdcr2 rdcr1 phase2 phase1 il2 il1 rpcb2 rpcb1 figure 13. current balancing circuit v isen1 r dcr1 r pcb1 + () i l1 = (eq. 5) v isen2 r dcr2 r pcb2 + () i l2 = (eq. 6)
isl62882, isl62882b 17 fn6890.4 june 21, 2011 sometimes, it is difficult to implement symmetrical layout. for the circuit figure 13 shows, asym metric layout causes different r pcb1 and r pcb2 thus current imbalance. figure 14 shows a differential-sensing current ba lancing circuit recommended for isl62882. the current sensing trac es should be routed to the inductor pads so they only pick up the inductor dcr voltage. each isen pin sees the average voltage of two sources: its own phase inductor phase-node pad, and the other phase inductor output side pad. equations 7 and 8 give the isen pin voltages: the isl62882 will make v isen1 = v isen2 . so there are: rewriting equation 9 gives: therefore: current balancing (i l1 = i l2 ) will be achieved when there is r dcr1 = r dcr2 . r pcb1 and r pcb2 will not have any effect. since the slave ripple capacitor voltages mimic the inductor currents, r 3 ? modulator can naturally achieve excellent current balancing during steady state an d dynamic operations. figure 15 shows current balancing performance of the isl62882 evaluation board with load transi ent of 15a/50a at different rep rates. the inductor currents follow the load current dynamic change with the output capacitors supplying the difference. the inductor currents can track the load current well at a low rep rate, but cannot keep up when the rep rate gets into the hundred-khz range, where it?s out of the cont rol loop bandwidth. the controller achieves excellent current balancing in all cases. figure 14. differential-sensing current balancing circuit internal to ic v o isen2 rs cs isen1 rs cs l2 l1 rdcr2 rdcr1 phase2 phase1 i l2 i l1 rpcb2 rpcb1 rs rs v2p v2n v1p v1n v isen1 v 1p v 2n + = (eq. 7) v isen2 v 2p v 1n + = (eq. 8) v 1p v 2n + v 2p v 1n + = (eq. 9) v 1p v 1n ? v 2p v 2n ? = (eq. 10) r dcr1 i l1 r dcr2 i l2 = (eq. 11) figure 15. isl62882 evaluation board current balancing during dynamic operation. ch1: il1, ch2: i ioad , ch3: il2 rep rate = 10khz rep rate = 25khz rep rate = 50khz rep rate = 100khz rep rate = 200khz
isl62882, isl62882b 18 fn6890.4 june 21, 2011 ccm switching frequency the r fset resistor between the comp and the vw pins sets the vw windows size, therefore sets the switching frequency. when the isl62882 is in continuous conduction mode (ccm), the switching frequency is not absolutely constant due to the nature of the r 3 ? modulator. as explained in the ?multiphase r 3 ? modulator? on page 12, the effective switching frequency will increase during load insertion and will decrease during load release to achieve fast response. on the other hand, the switching frequency is relatively constant at steady state. variation is expected when the power stage condition, such as input voltage, output voltage, load, etc. changes. the variation is usually less than 15% and doesn?t have any significant effect on output voltage ripple magnitude. equation 12 gives an estimate of the frequency-setting resistor r fset value. 8k r fset gives approximately 300khz switching frequency. lower resistance gives higher switching frequency. modes of operation the isl62882 can be configured for 2- or 1-phase operation. for 1-phase configuration, tie the isen2 pin to 5v. in this configuration, only phase-1 is active. table 2 shows the isl62882 configurations, programmed by the isen2 pin status and the rbias value. if the isen2 pin is connected to the power stage, the isl62882 is in 2-phase cpu vr configuration. rbias = 147k disables the overshoot reduction function and rbias = 47k enables it. if isen2 is tied to 5v, the is l62882 is configured for 1-phase operation. rbias = 147k sets 1-phase cpu vr configuration and rbias = 47k sets 1-phase gpu configuration. table 3 shows the isl62882 operat ional modes, programmed by the logic status of the psi# and dprslpvr pins. in 2-phase configurat ion, the isl62882 enters 1-phase ccm for (psi# = 0 and dprslpvr = 0). it drops phase 2 and reduces the overcurrent and the way-overcurrent protection levels to 1/2 of the initial values. the isl62882 enters 1-phase de mode when dprslpvr = 1 by dropping phase 2. in 1-phase configurat ion, the isl62882 does not change the operational mode when the psi# si gnal changes status. it enters 1-phase de mode when dlprslpvr = 1. dynamic operation when the isl62882 is configured for cpu vr application, it responds to vid changes by sl ewing to the new voltage at 5mv/s slew rate. as the output approaches the vid command voltage, the dv/dt moderates to prevent overshoot. geyserville-iii transitions commands one lsb vid step (12.5mv) every 2.5s, controlling the effective dv/d t at 5mv/s. the isl62882 is capable of 5mv/s slew rate. when the isl62882 is configured for gpu vr application, it responds to vid changes by slewin g to the new voltage at a slew rate set by the logic status on the dprslpvr pin. the slew rate is 5mv/s when dprslpvr = 0 and is doubled when dprslpvr = 1. when the isl62882 is in de mode, it will actively drive the output voltage up when the vid changes to a higher value. it?ll resume de mode operation afte r reaching the new voltage level. if the load is light enough to warrant dcm, it will enter dcm after the inductor current has crossed zero for four consecutive cycles. the isl62882 will remain in de mo de when the vid changes to a lower value. the output voltage will decay to the new value and the load will determine the slew rate. over-voltage protection is blanked during vid down transition in de mode until the output voltage is within 60mv of the vid value. during load insertion response, th e fast clock function increases the pwm pulse response speed. the isl62882 monitors the vsen pin voltage and compares it to 100ns-filtered version. when the unfiltered version is 20mv below the filtered version, the controller knows there is a fast voltage dip due to load insertion, hence issues an addi tional master clock signal to deliver a pwm pulse immediately. the r 3 ? modulator intrinsically has voltage feed-forward. the output voltage is insensitive to a fast slew rate input voltage change. protections the isl62882 provides overcurrent, current-balance, undervoltage, overvoltage, and over-temperature protections. the isl62882 determines overcurrent protection (ocp) by comparing the average value of the droop current i droop with an internal current source thresh old. it declares ocp when i droop is above the threshold for 120s. a resistor r comp from the comp pin to gnd programs the ocp current source threshold, as well table 2. isl62882 configurations isen2 rbias (k ) configuration overshoot reduction function connected to the power stage 147 2-phase cpu vr disabled 47 enabled tied to 5v 147 1-phase cpu vr see table 4 47 1-phase gpu vr table 3. isl62882 modes of operation config. psi# dprslpvr operational mode voltage slew rate 2-phase cpu configuration 0 0 1-phase ccm 5mv/s 011-phase de 1 0 2-phase ccm 111-phase de 1-phase cpu configuration x 0 1-phase ccm 11-phase de 1-phase gpu configuration x 0 1-phase ccm 11-phase de 10mv/s r fset k () period s () 0.29 ? () 2.65 = (eq. 12)
isl62882, isl62882b 19 fn6890.4 june 21, 2011 as the overshoot reduction function in 1-phase configuration, as table 4 shows. it is recommended to use the nominal r comp value. the isl62882 detects the r comp value at the beginning of start-up, and sets the internal ocp threshold accordingly. it remembers the r comp value until the vr_on signal drops below the por threshold. the default ocp threshold is the value when r comp is not populated. it is recommended to scale the droop current i droop such that the default ocp threshold gives approximately the desired ocp level, then use r comp to fine tune the ocp level if necessary. for overcurrent conditions abov e 2.5x the ocp level, the pwm outputs will immediately shut off and pgood will go low to maximize protection. this protecti on is also referred to as way- overcurrent protection or fast-o vercurrent protection, for short- circuit protections. the isl62882 monitors the isen pin voltages to determine current-balance protection. if the isen pin voltage difference is greater than 9mv for 1ms, the controller will declare a fault and latch off. the isl62882 will declare undervoltage (uv) fault and latch off if the output voltage is less than the vid set value by 300mv or more for 1ms. it?ll turn off the pwm outputs and de-assert pgood. the isl62882 has two levels of overvoltage protections. the first level of overvoltage protection is referred to as pgood overvoltage protection. if the output voltage exceeds the vid set value by +200mv for 1ms, the isl62882 will declare a fault and de-assert pgood. the isl62882 takes the same acti ons for all of the above fault protections: de-assertion of pgood and turn-off of the high-side and low-side power mosfets. any residual inductor current will decay through the mosfet body diodes. these fault conditions can be reset by bringing vr _on low or by bringing v dd below the por threshold. when vr_on and v dd return to their high operating levels, a soft-start will occur. the second level of overvoltage protec tion is different. if the output voltage exceeds 1.55v, the isl62882 will immediately declare an ov fault, de-assert pgood, and turn on the low-side power mosfets. the low-side power mosf ets remain on until the output voltage is pulled down below 0.85v when all power mosfets are turned off. if the output voltage rises above 1.55v again, the protection process is repeated. this behavior provides the maximum amount of protection against shorted high-side power mosfets while preventing output ringing below ground. resetting vr_on cannot clear the 1.55v ovp. only resetting v dd will clear it. the 1.55v ovp is active all the time when the controller is enabled, even if one of the other faults have been declared. this ensures that the processor is protected against high-side power mosfet leakage while the mosfets are commanded off. the isl62882 has a therma l throttling feature. if the voltage on the ntc pin goes below the 1.18v ot threshold, the vr_tt# pin is pulled low indicating the need for thermal throttling to the system. no other action is taken within the isl62882 in response to ntc pin voltage. table 5 summarizes the fault protections. table 4. isl62882 r comp programability r comp 2-phase config. 1-phase config. min (k ) nominal (k ) max (k ) ocp threshold (a) overshoot reduction function none none 40 20 disabled 320 400 480 45.3 22.7 210 235 260 41.3 20.7 155 165 175 36 18 104 120 136 37.33 20 enabled 78 85 92 38.7 22.7 62 66 70 42.7 20.7 45 50 55 44 18 table 5. fault protection summary fault type fault duration before protection protection action fault reset overcurrent 120s pwm tri-state, pgood latched low vr_on toggle or vdd toggle way-overcurrent (2.5xoc) <2s overvoltage +200mv 1ms undervoltage -300mv phase current unbalance overvoltage 1.55v immediately low-side mosfet on until v core <0.85v, then pwm tri-state, pgood latched low. vdd toggle over-temperature 1ms n/a
isl62882, isl62882b 20 fn6890.4 june 21, 2011 current monitor the isl62882 provides the current monitor function. the imon pin outputs a high-speed analog cu rrent source that is 3 times of the droop current flowing out of the fb pin. thus equation 13: as figures 1 and 2 show, a resistor r imon is connected to the imon pin to convert the imon pin current to voltage. a capacitor can be paralleled with r imon to filter the voltage information. the imvp-6.5? specification requir es that the imon voltage information be referenced to vss sense . the imon pin voltage range is 0v to 1.1v. a clamp circuit prevents the imon pin voltage from going above 1.1v. fb2 function the fb2 function is only ava ilable when the isl62882 is in 2- phase configuration. figure 16 shows the fb2 function . a switch (called fb2 switch) turns on to short the fb and the fb 2 pins when the controller is in 2-phase mode. capacitors c3.1 and c3.2 are in parallel, serving as part of the compensator. when the controller enters 1-phase mode, the fb2 switch turns off, removing c3.2 and leaving only c3.1 in the compensator. the compensator gain will increase with the removal of c3.2. by prop erly sizing c3.1 and c3.2, the compensator cab be optimal for both 2-phase mode and 1-phase mode. when the fb2 switch is off, c3.2 is disconnected from the fb pin. however, the controller still actively drives the fb2 pin voltage to follow the fb pin voltage such th at c3.2 voltage always follows c3.1 voltage. when the controller turns on the fb2 switch, c3.2 will be reconnected to the compensator smoothly. the fb2 function ensures excellent transient response in both 2-phase mode and 1-phase mode. if one decides not to use the fb2 function, simply populate c3.1 only. adaptive body diode conduction time reduction in dcm, the controller turns off the low-side mosfet when the inductor current approaches zero. during on-time of the low-side mosfet, phase voltage is negative and the amount is the mosfet r ds(on) voltage drop, which is proportional to the inductor current. a phase comparator inside the controller monitors the phase voltage during on-time of the low-side mosfet and compares it with a threshold to determine the zero-crossing point of the inductor current. if the inductor current has not reached zero when the lo w-side mosfet turns off, it?ll flow through the low-side mosfet body diode, causing the phase node to have a larger voltage drop until it decays to zero. if the inductor current has crossed zero and reversed the direction when the low-side mosfet turns off, it?ll flow through the high-side mosfet body diode, causing the phase node to have a spike until it decays to zero. th e controller continues monitoring the phase voltage after turning off the low-side mosfet and adjusts the phase comparator th reshold voltage accordingly in iterative steps such that the low-side mosfet body diode conducts for approximately 40ns to minimize the body diode-related loss. overshoot reduction function the isl62882 has an optional overshoot reduction function. tables 2 and 4 show to enable and disable it. when a load release occurs, the energy stored in the inductors will dump to the output capacitor, causing output voltage overshoot. the inductor current freewheels through the low-side mosfet during this period of time. the overshoot reduction function turns off the low-side mo sfet during the output voltage overshoot, forcing the inductor current to freewheel through the low-side mosfet body diode. since the body diode voltage drop is much higher than mosfet r dson voltage drop, more energy is dissipated on the low-side mosfet therefore the output voltage overshoot is lower. if the overshoot reduction function is enabled, the isl62882 monitors the comp pin voltage to determine the output voltage overshoot condition. the comp vo ltage will fall an d hit the clamp voltage when the output voltage overshoots. the isl62882 will turn off lgate1 and lgate2 when comp is being clamped. all the low-side mosfets in the power stage will be turned off. when the output voltage has reached its peak and starts to come down, the comp voltage starts to rise and is no longer clamped. the isl62882 will resume normal pwm operation. when psi# is low, indicating a low power state of the cpu, the controller will disable the oversh oot reduction function as large magnitude transient event is not expected and overshoot is not a concern. while the overshoot reduction func tion reduces the output voltage overshoot, energy is dissipated on the low-side mosfet, causing additional power loss. the more fr equent transient event, the more power loss dissipated on the low-side mosfet. the mosfet may face severe thermal stress when tr ansient events happen at a high repetitive rate. user discretion is advised when this function is enabled. key component selection r bias the isl62882 uses a resistor (1% or better tolerance is recommended) from the rbias pin to gnd to establish highly accurate reference current sources inside the ic. refer to table 2 to select the resistance according to desired configuration. do not connect any other components to this pin. do not connect any capacitor to the rbias pin as it will create instability. i imon 3i droop = (eq. 13) figure 16. fb2 function in 2-phase mode r1 e/a r3 c2 c1 vref r2 c3.2 c3.1 fb fb2 comp vsen r1 e/a r3 c2 c1 vref r2 c3.2 c3.1 fb fb2 comp vsen controller in 2-phase mode controller in 1-phase mode
isl62882, isl62882b 21 fn6890.4 june 21, 2011 care should be taken in layout that the resistor is placed very close to the rbias pin and that a good quality signal ground is connected to the opposite side of the r bias resistor. r is and c is as figures 1 thru 4 show, the isl62882 needs the r is -c is network across the isum+ and the isum- pins to stabilize the droop amplifier. the preferred values are r is = 82.5 and c is = 0.01f. slight deviations from the recommended values are acceptable. large deviations may result in instability. inductor dcr current-sensing network figure 17 shows the inductor dc r current-sensing network for a 2-phase solution. an inductor current flows through the dcr and creates a voltage drop. each inductor has two resistors in r sum and r o connected to the pads to accurately sense the inductor current by sensing the dcr voltage drop. the r sum and r o resistors are connected in a summing network as shown, and feed the total current information to the ntc network (consisting of r ntcs , r ntc and r p ) and capacitor c n . r ntc is a negative temperature coefficient (ntc) thermistor, used to temperature-compensate the inductor dcr change. the inductor output side pads are electrically shorted in the schematic, but have some parasitic impedance in actual board layout, which is why one cannot simply short them together for the current-sensing summing network. it is recommended to use 1 ~10 r o to create quality signals. since r o value is much smaller than the rest of the current sensing circuit, the following analysis will ignore it for simplicity. the summed inductor current information is presented to the capacitor c n . equations 14 thru 18 describe the frequency-domain relationship between inductor total current i o (s) and c n voltage v cn (s). where n is the number of phases. transfer function a cs (s) always has unity gain at dc. the inductor dcr value increases as the wi nding temperature increases, giving higher reading of the inductor dc current. the ntc r ntc values decreases as its temp erature decreases. proper selections of r sum , r ntcs , r p and r ntc parameters ensure that v cn represent the inductor total dc current over the temperature range of interest. there are many sets of parameters that can properly temperature-compensate the dcr change. since the ntc network and the r sum resistors form a voltage divider, v cn is always a fraction of the inductor dcr voltag e. it is recommended to have a higher ratio of v cn to the inductor dcr voltage, so the droop circuit has higher signal level to work with. a typical set of parameters that provide good temperature compensation are: r sum = 3.65k , r p = 11k , r ntcs =2.61k and r ntc = 10k (ert-j1vr103j). the ntc network parameters may need to be fine tuned on actual boards. one can apply full load dc current and record the output voltage reading immediately; then record the ou tput voltage reading again when the board has reached the thermal steady state. a good ntc network can limit the output voltage drift to within 2mv. it is recommended to follow the intersil evaluation board layout and current-sensing network paramete rs to minimize engineering time. v cn (s) also needs to represent real-time i o (s) for the controller to achieve good transient response. transfer function a cs (s) has a pole sns and a zero l . one needs to match l and sns so a cs (s) is unity gain at all frequencies. by forcing l equal to sns and solving for the solution, equation 19 gives c n value. figure 17. dcr current-sensing network cn rsum ro rntcs rntc rp dcr l dcr l rsum ro phase1 phase2 io ri isum+ isum- vcn v cn s () r ntcnet r ntcnet r sum n -------------- + ----------------------------------------- dcr n ----------- - ?? ?? ?? ?? ?? i o s () a cs s () = (eq. 14) r ntcnet r ntcs r ntc + () r p r ntcs r ntc r p ++ -------------------------------------------------- - = (eq. 15) a cs s () 1 s l ------ + 1 s sns ------------ + ---------------------- = (eq. 16) l dcr l ----------- - = (eq. 17) sns 1 r ntcnet r sum n -------------- r ntcnet r sum n -------------- + ----------------------------------------- c n ------------------------------------------------------ = (eq. 18) c n l r ntcnet r sum n -------------- r ntcnet r sum n -------------- + ----------------------------------------- dcr ----------------------------------------------------------- - = (eq. 19)
isl62882, isl62882b 22 fn6890.4 june 21, 2011 for example, given n = 2, r sum = 3.65k , r p = 11k , r ntcs =2.61k , r ntc = 10k , dcr = 0.88m and l = 0.36h, equation 19 gives c n = 0.294f. assuming the compensator design is correct, figure 18 shows the expected load transient response waveforms if c n is correctly selected. when the load current i core has a square change, the output voltage v core also has a square response. if c n value is too large or too small, v cn (s) will not accurately represent real-time i o (s) and will worsen the transient response. figure 19 shows the load transient response when c n is too small. v core will sag excessively upon load insertion and may create a system failure. figure 20 shows the transient response when c n is too large. v core is sluggish in drooping to its final value. there will be excessive overshoot if load insertion occurs during this time, which may potentially hurt the cpu reliability. figure 21 shows the output voltage ring back problem during load transient response. the load current i o has a fast step change, but the inductor current i l cannot accurately follow. instead, i l responds in first order system fash ion due to the nature of current loop. the esr and esl effect of the output capacitors makes the output voltage v o dip quickly upon load current change. however, the controller regulates v o according to the droop current i droop , which is a real-time representation of i l ; therefore it pulls v o back to the level dictated by i l , causing the ring back problem. this phenomenon is not observed when the output capacitor have very low esr and esl, such as all ceramic capacitors. figure 22 shows two optional circui ts for reduction of the ring back. c n is the capacitor used to match the inductor time constant. it usually takes the parallel of two (or more) capacitors to get the desired value. figure 22 shows that two capacitors c n.1 and c n.2 are in parallel. resistor r n is an optional co mponent to reduce the v o ring back. at steady state, c n.1 + c n.2 provides the desired c n capacitance. at the beginning of i o change, the effective capacitance is less because r n increases the impedance of the c n.1 branch. as figure 19 explains, v o tends to dip when c n is too small, and this effect will reduce the v o ring back. this effect is more pronounced when c n.1 is much larger than c n.2 . it is also more pronounced when r n is bigger. however, the presence of r n increases the ripple of the v n signal if c n.2 is too small. it is recommended to keep c n.2 greater than 2200pf. r n value usually is a few ohms. c n.1 , c n.2 and r n values should be determined through tuning th e load transient response waveforms on an actual board. figure 18. desired load transient response waveforms o i v o figure 19. load transient response when c n is too small o i v o figure 20. load transient response when c n is too large o i v o figure 21. output voltage ring back problem o i v o l i ring back figure 22. optional circuits for ring back reduction cn.2 rntcs rntc rp ri isum+ isum- rip cip optional vcn cn.1 rn optional
isl62882, isl62882b 23 fn6890.4 june 21, 2011 r ip and c ip form an r-c branch in parallel with r i , providing a lower impedance path than r i at the beginning of i o change. r ip and c ip do not have any effect at steady state. through proper selection of r ip and c ip values, i droop can resemble i o rather than i l , and v o will not ring back. the recommended value for r ip is 100 . c ip should be determined through tuning the load transient response waveforms on an actual board. the recommended range for c ip is 100pf~2000pf. however, it should be noted that the r ip -c ip branch may distort the i droop waveform. instead of being triangular as the real inductor current, i droop may have sharp spikes, which may adversely affect i droop average value detection and therefore may affect ocp accuracy. user discretion is advised. resistor current-sensing network figure 23 shows the resistor current-sensing network for a 2-phase solution. each inductor has a series current-sensing resistor r sen . r sum and r o are connected to the r sen pads to accurately capture the inductor current information. the r sum and r o resistors are connected to capacitor c n . r sum and c n form a filter for noise attenuation. equations 20 thru 22 give v cn (s) expression transfer function a rsen (s) always has unity gain at dc. current- sensing resistor r sen value will not have significant variation over-temperature, so there is no need for the ntc network. the recommended values are r sum = 1k and c n = 5600pf. overcurrent protection refer to equation 1 on page 16 and figures 12, 17 and 23; resistor r i sets the droop current i droop . table 4 shows the internal ocp threshold. it is recommended to design i droop without using the r comp resistor. for example, the ocp threshold is 40a for 2-phase solution. we will design i droop to be 34.3a at full load, so the ocp trip level is 1.16x of the full load current. for inductor dcr sensing, equation 23 gives the dc relationship of v cn (s) and i o (s). substitution of equation 23 into equation 1 gives equation 24: therefore: substitution of equation 15 and application of the ocp condition in equation 25 gives equation 26: where i omax is the full load current, i droopmax is the corresponding droop current. for example, given n = 2, r sum =3.65k , r p = 11k , r ntcs = 2.61k , r ntc = 10k , dcr = 0.88m , i omax = 51a and i droopmax = 34.3a, equation 26 gives r i = 998 . for resistor sensing, equation 27 gives the dc relationship of v cn (s) and i o (s). substitution of equation 27 in to equation 1 gives equation 28: therefore substitution of equation 29 and application of the ocp condition in equation 25 gives equation 30: figure 23. resistor current-sensing network cn rsum ro dcr l dcr l rsum ro phase1 phase2 io ri isum+ isum- vcn rsen rsen v cn s () r sen n ------------ i o s () a rsen s () = (eq. 20) a rsen s () 1 1 s sns ------------ + ---------------------- = (eq. 21) rsen 1 r sum n -------------- c n --------------------------- = (eq. 22) v cn r ntcnet r ntcnet r sum n -------------- + ----------------------------------------- dcr n ----------- - ?? ?? ?? ?? ?? i o = (eq. 23) i droop 2 r i ---- - r ntcnet r ntcnet r sum n -------------- + ----------------------------------------- dcr n ----------- - i o = (eq. 24) r i 2r ntcnet dcr i o nr ntcnet r sum n -------------- + ?? ?? i droop ------------------------------------------------------------------------------- - = (eq. 25) r i 2 r ntcs r ntc + () r p r ntcs r ntc r p ++ -------------------------------------------------- - dcr i omax n r ntcs r ntc + () r p r ntcs r ntc r p ++ -------------------------------------------------- - r sum n -------------- + ?? ?? ?? i droopmax ------------------------------------------------------------------------------------------------------------------------- = (eq. 26) v cn r sen n ------------ i o = (eq. 27) i droop 2 r i ---- - r sen n ------------ i o = (eq. 28) r i 2r sen i o ni droop --------------------------- = (eq. 29) r i 2r sen i omax ni droopmax -------------------------------------- = (eq. 30)
isl62882, isl62882b 24 fn6890.4 june 21, 2011 where i omax is the full load current, i droopmax is the corresponding droop current. for example, given n = 2, r sen =1m , i omax = 51a and i droopmax = 34.3a, equation 30 gives r i = 1.487k . a resistor from comp to gnd can adjust the internal ocp threshold, providing another dimension of fine-tune flexibility. table 4 shows the detail. it is recommended to scale i droop such that the default ocp threshold gives approximately the desired ocp level, then use r comp to fine tune the ocp level if necessary. load line slope refer to figure 12. for inductor dcr sensing, substitution of equation 24 into equation 2 gives the load line slope expression: for resistor sensing, substitution of equation 28 into equation 2 gives the load line slope expression : substitution of equation 25 and rewriting equation 31, or substitution of equation 29 and rewriting equation 32 give the same result in equation 33: one can use the full load condition to calculate r droop . for example, given i omax = 51a, i droopmax = 34.3a and ll = 1.9m , equation 33 gives r droop = 2.825k . it is recommended to start with the r droop value calculated by equation 33, and fine tune it on the actual board to get accurate load line slope. one should record the output volt age readings at no load and at full load for load line slope calculation. reading the output voltage at lighter load instead of full load will increase the measurement error. current monitor refer to equation 13 for the imon pin current expression. refer to figures 1 and 2, the imon pin current flows through r imon . the voltage across r imon is expressed in equation 34: rewriting equation 33 gives equation 35: substitution of equation 35 into equation 34 gives equation 36: rewriting equation 36 and applicat ion of full load condition gives equation 37: for example, given ll = 1.9m , r droop = 2.825k , v rimon = 963mv at i omax = 51a, equation 37 gives r imon =9.358k . a capacitor c imon can be paralleled with r imon to filter the imon pin voltage. the r imon c imon time constant is the user?s choice. it is recommended to have a time co nstant long enough such that switching frequency ripples are removed. compensator figure 18 shows the desired load transient response waveforms. figure 24 shows the equivalent circuit of a voltage regulator (vr) with the droop function. a vr is equivalent to a voltage source (= vid) and output impedance z out (s). if z out (s) is equal to the load line slope ll, i.e., constant output impedance, in the entire frequency range, v o will have square response when i o has a square change. intersil provides a microsoft excel-based spreadsheet to help design the compensator and the cu rrent sensing network, so the vr achieves constant output impedance as a stable system. figure 27 shows a screenshot of the spreadsheet. a vr with active droop function is a dual-loop system consisting of a voltage loop and a droop loop wh ich is a current loop. however, neither loop alone is sufficient to describe the entire system. the spreadsheet shows two loop gain transfer functions, t1(s) and t2(s), that describe the entire system. figure 25 conceptually shows t1(s) measurement set-up and figure 26 conceptually shows t2(s) measurement set-up. the vr senses the inductor current, multiplies it by a gain of the load line slope, then adds it on top of the sensed output voltage and feeds it to the compensator. t(1) is measured after the summing node, and t2(s) is measured in the voltage loop before the summing node. the spreadsheet gives both t1(s) and t2(s) plots. however, only t2(s) can be actually measured on an isl62882 regulator. t1(s) is the total loop gain of the voltage loop and the droop loop. it always has a higher crossover frequency than t2(s) and has more meaning of system stability. t2(s) is the voltage loop gain with closed droop loop. it has more meaning of output voltage response. design the compensator to get stable t1(s) and t2(s) with sufficient phase margin, and output impedance equal or smaller than the load line slope. ll v droop i o ----------------- - 2r droop r i ---------------------- r ntcnet r ntcnet r sum n -------------- + ----------------------------------------- dcr n ----------- - == (eq. 31) ll v droop i o ----------------- - 2r sen r droop nr i ----------------------------------------- == (eq. 32) r droop i o i droop --------------- - ll = (eq. 33) v rimon 3i droop r imon = (eq. 34) i droop i o r droop ------------------ ll = (eq. 35) v rimon 3i o ll r droop -------------------- - r imon = (eq. 36) r imon v rimon r droop 3i o ll -------------------------------------------- = (eq. 37) figure 24. voltage regulator equivalent circuit o i v o vid z out (s) = ll load vr
isl62882, isl62882b 25 fn6890.4 june 21, 2011 figure 25. loop gain t1 (s) measurement set-up q2 q1 l o i c out v o v in gate driver comp mod. load line slope ea vid channel b channel a excitation output isolation transformer 20 loop gain = channel b channel a network analyzer figure 26. loop gain t2 (s) measurement set-up q2 q1 l o i c out v o v in gate driver comp mod. load line slope ea vid channel b channel a excitation output isolation transformer 20 loop gain = channel b channel a network analyzer
isl62882, isl62882b 26 fn6890.4 june 21, 2011 jia wei, jwei@intersil.com, 919-405-3605 attention: 1. "analysis toolpak" add-in is required. to turn on, go to tools--add-ins, and check "analysis toolpak" . 2. green cells require user input controller part number: phase number: 2 vin: 12 volts vo: 1.15 volts full load current: 50 amps estimated full-load efficiency: 87 % number of output bulk capacitors: 3 capacitance of each output bulk capacitor: 470 uf esr of each output bulk capacitor: 4.5 m r1 2.870 k r1 2.87 k esl of each output bulk capacitor: 0.6 nh r2 387.248 k r2 412 k number of output ceramic capacitors: 30 r3 0.560 k r3 0.562 k capacitance of each output ceramic capacitor: 10 uf c1 188.980 pf c1 150 pf esr of each output ceramic capacitor: 3 m c2 498.514 pf c2 390 pf esl of each output ceramic capacitor: 3 nh c3 32.245 pf c3 32 pf switching frequency: 300 khz inductance per phase: 0.36 uh cpu socket resistance: 0.9 m desired load-line slope: 1.9 m desired isum- pin current at full load: 33.1 ua t1 bandwidth: 190khz t2 bandwidth: 52khz (this sets the over-current protection level) t1 phase margin: 63.4 t2 phase margin: 94.7 inductor dcr 0.88 m place the 2nd compensator pole fp2 at: 1.9 rsum 3.65 k tune ki to get the desired loop gain bandwidth rntc 10 k tune the compensator gain factor ki: 1.15 rntcs 2.61 k (recommended ki range is 0.8~2) rp 11 k recommended value user selected value cn 0.294 uf cn 0.294 uf ri 1014.245 ri 1000 operation parameters use user-selected value (y/n)? performance and stability x fs (switching frequency) changing the settings in red requires deep understanding of control loop design compensator parameters current sensing network parameters compensation & current sensing network design for intersil multiphase r^3 regulators for imvp-6.5 recommended value user-selected value operation parameters loop gain, gain curve

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2 1 2 1 2 1 2 1 2 1 2 1 ) ( p p z z i v f s f s s f s f s i k s a loop gain, phase curve " ) )

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isl62882, isl62882b 27 fn6890.4 june 21, 2011 optional slew rate co mpensation circuit for 1-tick vid transition during a large vid transition, the dac steps through the vids at a controlled slew rate. for example, the dac may change a tick (12.5mv) per 2.5s per, controlling output voltage v core slew rate at 5mv/s. figure 28 shows the waveforms of 1-tick vid transition. during 1-tick vid transition, the dac ou tput changes at approximately 15mv/s slew rate, but the dac cannot step through multiple vids to control the slew rate. instead, the control loop response speed determines v core slew rate. ideally, v core will follow the fb pin voltage slew rate. however, the controller senses the inductor current increase during th e up transition, as the i droop_vid waveform shows, and will droop the output voltage v core accordingly, making v core slew rate slow. similar behavior occurs during the down transition. to control v core slew rate during 1-tick vid transition, one can add the r vid -c vid branch, whose current i vid cancels i droop_vid . when v core increases, the time do main expression of the induced i droop change is where c out is the total output capacitance. in the mean time, the r vid -c vid branch current i vid time domain expression is: it is desired to let i vid (t) cancel i droop_vid (t). so there are: and: the result is expressed in equation 42: and: for example: given ll = 1.9m , r droop = 2.87k , c out = 1710f, dv core /dt = 5mv/s and dv fb /dt = 15mv/s, equation 42 gives r vid = 2.87k and equation 43 gives c vid = 377pf. it?s recommended to select the calculated r vid value and start with the calculated c vid value and tweak it on the actual board to get the best performance. during normal transient response, the fb pin voltage is held constant, therefore is virtual grou nd in small signal sense. the r vid - c vid network is between the virtual ground and the real ground, and hence has no effect on transient response. voltage regulator thermal throttling figure 28. optional slew ra te compensation circuit for1-tick vid transition x 1 e/a dac vid<0:6> rdroop idroop_vid vdac fb comp vcore vsssense vids rtn vss internal to ic rvid cvid vid<0:6> vfb vcore ivid idroop_vid ivid optional i droop t () c out ll r droop ------------------------ dv core dt ----------------- - 1e t ? c out ll ------------------------- ? ?? ?? ?? ?? = (eq. 38) i vid t () c vid dv fb dt ----------- - 1e t ? r vid c vid ------------------------------ ? ?? ?? ?? ?? = (eq. 39) c vid dv fb dt ----------- - c out ll r droop ------------------------ dv core dt ----------------- - = (eq. 40) r vid c vid c out ll = (eq. 41) r vid r droop = (eq. 42) c vid c out ll r droop ------------------------ dv core dt ----------------- - dv fb dt ----------- - ----------------- - = (eq. 43) ntc r ntc - + v ntc - + vr_tt# 1.24v 54a internal to isl62882 figure 29. circuitry associated with the thermal throttling feature of the isl62882 r s 64a 1.20v sw1 sw2
isl62882, isl62882b 28 fn6890.4 june 21, 2011 figure 29 shows the thermal thro ttling feature with hysteresis. an ntc network is connected between the ntc pin and gnd. at low temperature, sw1 is on and sw2 connects to the 1.20v side. the total current flowing out of the ntc pin is 60a. the voltage on ntc pin is higher than threshold voltage of 1.20v and the comparator output is low. vr_tt# is pulled up by the external resistor. when temperature increases, th e ntc thermistor resistance decreases so the ntc pin voltage drops. when the ntc pin voltage drops below 1.20v, the co mparator changes polarity and turns sw1 off and throws sw2 to 1.24v. this pulls vr_tt# low and sends the signal to start th ermal throttle. there is a 6a current reduction on ntc pin and 40mv voltage increase on threshold voltage of the comparator in this state. the vr_tt# signal will be used to change the cpu operation and decrease the power consumption. when th e temperature drops down, the ntc thermistor voltage will go up. if ntc voltage increases to above 1.24v, the comparator w ill flip back. the external resistance difference in thes e two conditions is shown in equation 44: one needs to properly select the ntc thermistor value such that the required temperature hysteresis correlates to 2.96k resistance change. a regular resistor may need to be in series with the ntc thermistor to meet the threshold voltage values. for example, given panasonic ntc thermistor with b = 4700, the resistance will drop to 0.03322 of its nominal at +105c, and drop to 0.03956 of its nominal at +100c. if the required temperature hysteresis is +105c to +100c, the required resistance of ntc will be as shown in equation 45: therefore, a larger value thermistor such as 470k ntc should be used. at +105c, 470k ntc resistance becomes (0.03322 470k ) = 15.6k . with 60a on the ntc pin, the voltage is only (15.6k 60a) = 0.937v. this value is much lower than the threshold voltage of 1.20v. therefore, a regular resistor needs to be in series with the ntc. the required resistance can be calculated by equation 46: 4.42k is a standard resistor value. therefore, the ntc branch should have a 470k ntc and 4.42k resistor in series. the part number for the ntc thermistor is ertj0ev474j. it is a 0402 package. ntc thermistor will be placed in the hot spot of the board. current balancing refer to figures 1 and 2. the isl62882 achieves current balancing through matching the isen pin voltages. r s and c s form filters to remove the switching ripple of the phase node voltages. it is recommended to use rather long r s c s time constant such that the isen vo ltages have minimal ripple and represent the dc current flowing through the inductors. recommended values are r s = 10k and c s = 0.22f. layout guidelines table 6 shows the layout consider ations. the designators refer to the reference design shown in figure 31. 1.24v 54 a --------------- 1.20v 60 a --------------- ? 2.96k = (eq. 44) (eq. 45) 2.96k 0.03956 0.03322 ? ( ) ------------------------------------------------------- 467k = (eq. 46) 1.20v 60 a --------------- 15.6k ? 4.4k = table 6. layout consideration pin name layout consideration ep gnd create analog ground plane underneath the controller and the anal og signal processing components. don?t let the power ground plane overlap with the analog ground plane. avoid noisy planes/traces (e.g.: phase node) from crossing over/overlapping with the analog plane. 1 pgood no special consideration 2 psi# no special consideration 3rbiasplace the r bias resistor (r16) in general proximity of the controller. low impedance connection to the analog ground plane. 4 vr_tt# no special consideration 5 ntc the ntc thermistor (r9) needs to be placed close to the thermal source that is monitor to determine thermal throttling. usually it?s placed close to phase-1 high-side mosfet. 6 vw place the capacitor (c4) across vw and comp in close proximity of the controller 7 comp place the compensator components (c3, c5, c6 r7, r11, r10 and c11) in general proximity of the controller. 8fb 9fb2 10 isen2 a capacitor (c9) decouples it to vsum-. place it in general proximity of the controller. 11 isen1 a capacitor (c10) decouples it to vsum-. place it in general proximity of the controller. 12 vsen place the vsen/rtn filter (c12, c13) in close proximity of the controller for good decoupling. 13 rtn
isl62882, isl62882b 29 fn6890.4 june 21, 2011 14 isum- place the current se nsing circuit in general proximity of the controller. place c82 very close to the controller. place ntc thermistors r42 next to phase-1 inductor (l1) so it senses the inductor temperature correctly. each phase of the power stage sends a pair of vsum+ and vsum- signals to the controller. run these two signals traces in parallel fashion with decent width (>20mil). important: sense the inductor current by routing the sensing circuit to the inductor pads. route r63 and r71 to the phase-1 side pad of inductor l1. route r88 to the output side pad of inductor l1. route r65 and r72 to the phase-2 side pad of inductor l2. route r90 to the output side pad of inductor l2. if possible, route the traces on a different layer from the inductor pad layer and use vias to connect the traces to the center of the pads. if no via is allowed on the pad, consider routing the traces into the pads from the inside of the inductor. the following drawings show the two preferred ways of routing current sensing traces. 15 isum+ 16 vdd a capacitor (c16) decouples it to gnd. place it in close proximity of the controller. 17 vin a capacitor (c17) decouples it to gnd. place it in close proximity of the controller. 18 imon place the filter capacitor (c21) close to the cpu. 19 boot1 use decent wide trace (>30mil). avoid any sensitive analog signal trac e from crossing over or getting close. 20 ugate1 run these two traces in parallel fashion with decent width (>30mil). avoid any sensitive analog signal trace from crossing over or getting close. recommend routing phase1 trace to the phase-1 high-side mosfet (q2 and q8) source pins instead of general phase-1 node copper. 21 phase1 22 vssp1 run these two traces in parallel fashion with decent width (>30mil). avoid any sensitive analog signal trace from crossing over or getting close. recommend routing vssp1 to the phase-1 low-side mosfet (q3 and q9) source pins instead of general power ground plane for better performance. 23 lgate1a 24 lgate1b 25 vccp a capacitor (c22) decouples it to gnd. place it in close proximity of the controller. table 6. layout consideration (continued) pin name layout consideration inductor current-sensing traces vias inductor current-sensing traces 26 lgate2 run these two traces in parallel fashion with decent width (>30mil). avoid any sensitive analog signal trace from crossing over or getting close. recommend routing vssp2 to the phase-2 low- side mosfet (q5 and q1) source pins instead of general power ground plane for better performance. 27 vssp2 28 phase2 run these two traces in parallel fashion with decent width (>30mil). avoid any sensitive analog signal trace from crossing over or getting close. recommend routing phase2 trace to the phase-2 high-side mosfet (q4 an d q10) source pins instead of general phase-2 node copper. 29 ugate2 30 boot2 use decent wide trace (>30mil). avoid any sensitive analog signal trac e from crossing over or getting close. 31~37 vid0~6 no special consideration. 38 vr_on no special consideration. 39 dprslpvr no special consideration. 40 clk_en# no special consideration. other phase node minimize phase node copper area. don?t let the phase node copper overlap with/getting close to other sensitive traces. cut the power ground plane to avoid overlapping with phase node copper. other minimize the loop consisting of input capacitor, high-side mosfets and low-side mosfets (e.g., c27, c33, q2, q8, q3 and q9). table 6. layout consideration (continued) pin name layout consideration
isl62882, isl62882b 30 fn6890.4 june 21, 2011 47.5k optional ---- -------- dnp ---- ------------ layout note: 0.01uf 2.3mohm 0.88uh 4mohm 470uf 0.01uf ---- 422k 10k 1-phase, dcr sensing isl62881 gpu reference design jia wei 1of1 3/16/2009 optional 0.1uf ---- 3.01k 270pf 2.37k 6.98k ---- 100pf dnp dnp ---- 1000pf ---- dnp place near l1 3.65k 0.056uf 0.15uf 2.61k ntc 10k 11k -----> ------------ optional dnp optional ----- 330pf 82.5 ----- route ugate trace in parallel with the phase trace going to the source of q2 route lgate trace in parallel with the vssp trace going to the source of q3 22.6k irf7832 irf7821 irf7832 22uf 22uf 22uf 22uf 22uf 22uf 22uf 22uf 499 -------- ----- dnp ------- ---- ------- 15pf ------------ dnp ---- ------- ------- ------------ optional r110 r30 r26 c52 vr_on dprslpvr vid5 vid3 vid6 vid2 vid0 vid1 vid4 vr_tt# +1.1v pgood +3.3v +5v c20 r63 vsssense vin r10 56uf c24 10uf c27 10uf c33 vcore q3 q9 c61 c60 c59 c41 c40 c56 c55 c54 q2 l1 0 r56 0.22uf u6 r11 r7 c3 c83 c12 r20 r16 c21 r50 r40 0 vin r37 1 c17 0.22uf 1uf r41 r42 r38 c18 c82 c15 r109 c81 imon +5v c13 r18 10 vsssense 10 vccsense vcore c16 r17 1uf c6 c11 0 r12 r19 1.91k r4 1000pf c4 r6 r8 r9 isl62882hrz c30 c22 ep rbias phase1 boot pgood psi# vr_tt# ntc comp vw fb fb2 isen2 vid3 vid4 vid6 vr_on dprslpvr clk_en# ugate2 boot2 phase2 vssp2 lgate2 vccp lgate1b lgate1a ugate1 imon vdd vin isum+ isum- rtn vsen isen1 vssp1 vid0 vid1 vid2 vid5 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 out out in in in in in in in in in out in in in in in in in in in in in figure 30. 1-phase gpu appl icaton reference design
isl62882, isl62882b 31 fn6890.4 june 21, 2011 8.06k ------- ------- dnp dnp 0.01uf ------------- ---- dnp optional ---- ---- 1 with the phase1 trace going to route lgate1 trace in parallel same rule applies to other phases ---- ----- ---- ---- ----------- 100 ---- 1200pf ----- 1000pf 330pf 0.33uf 10uf 10uf 10uf 10uf 10uf 10uf route ugate1 trace in parallel 10uf irf7832 irf7821 irf7832 10uf 10uf 10uf 10uf 10uf 3.65k 10uf 10uf 10uf 10uf 10uf 10uf 10uf 0.36uh 82.5 11k 10k 10uf 10uf 10uf 10uf 10uf 10uf 10uf 9.31k -----> 412k 150pf 562 390pf 10uf 10uf 10uf 0.01uf 1 ntc 0.1uf 2.61k with the vssp1 trace going to 3.65k layout note: the source of q2 and q8 the source of q3 and q9 0.22uf 1k 10pf irf7821 irf7821 irf7832 0.36uh 10uf irf7832 470uf 470uf 470uf irf7821 dnp 22pf optional ----- 1of1 jia wei isl62882 reference design 0.22uf 2.87k 560pf ------------- ---- optional 0.047uf place near l1 2.87k ----------- optional 2-phase, dcr sensing july 2009 vid1 +5v 1uf imon c13 c12 r17 c18 u6 q2 vsum+ isen2 c52 r56 vr_on c42 c53 c54 c55 c56 r63 0.22uf l1 c20 r16 r9 c5 c6 r38 c82 r30 r37 r50 c21 r109 vsssense vsum+ r88 q8 isen2 isen1 10 1 10k r71 r65 10k r72 r90 c81 r7 10 r26 c17 c4 r6 vid4 vid0 vid2 r40 0 r42 vid6 vid5 c25 56uf 56uf c24 c44 c57 l2 q10 q11 c34 10uf 10uf c28 q4 c31 0 r57 c33 10uf q9 c30 r18 0 vin c39 c27 q5 0.22uf c3 vcore 0 vsum+ r41 vccsense r12 10uf +1.1v 0.22uf c16 c22 q3 1uf psi# +5v vin c15 vsum- isen1 vsum- c40 c41 c43 c47 c48 c49 c50 c59 c60 c61 c62 c63 c64 c65 c66 c67 c68 c69 c70 c71 c72 c73 c74 c75 c78 r20 vsssense vid3 isl62882hrz r4 c9 c11 r10 pgood +3.3v vr_tt# r110 c83 r8 499 vsum- c10 r11 vcore 1000pf 147k clk_en# dprslpvr 1.91k r23 1.91k r19 in page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 ep rbias phase1 boot pgood psi# vr_tt# ntc comp vw fb fb2 isen2 vid3 vid4 vid6 vr_on dprslpvr clk_en# ugate2 boot2 phase2 vssp2 lgate2 vccp lgate1b lgate1a ugate1 imon vdd vin isum+ isum- rtn vsen isen1 vssp1 vid0 vid1 vid2 vid5 out out in in in in in in in out in in out out out in out out in out in in in in in in in in out in in out in in figure 31. 2-phase cpu a pplication reference design
isl62882, isl62882b 32 fn6890.4 june 21, 2011 1-phase gpu application referenc e design bill of materials qty reference value description manufacturer part number package 1 c11 270pf multilayer cap, 16v, 10% generic h1045-00271-16v10 sm0603 1 c12 330pf multilayer cap, 16v, 10% generic h1045-00331-16v10 sm0603 1 c13 1000pf multilayer cap, 16v, 10% generic h1045-00102-16v10 sm0603 1 c15 0.01f multilayer cap, 16v, 10% generic h1045-00103-16v10 sm0603 2 c16,c22 1f multilayer cap, 16v, 20% generic h1045-00105-16v20 sm0603 1 c18 0.15f multilayer cap, 16v, 10% generic h1045-00154-16v10 sm0603 1 c20 0.1f multilayer cap, 16v, 10% generic h1045-00104-16v10 sm0603 3 c17, c21, c30 0.22f multilayer cap, 25v, 10% generic h1045-00224-25v10 sm0603 1 c24 56f radial sp series cap, 25v, 20% sanyo 25sp56m case-cc 2 c27,c33 10f multilayer cap, 25v, 20% generic h1065-00106-25v20 sm1206 1 c3 100pf multilayer cap, 16v, 10% generic h1045-00101-16v10 sm0603 1 c52 470f spcap, 2v, 4m polymer cap, 2.5v, 4.5m panasonic kemet eexsx0d471e4 t520v477m2r5a(1)e4r5-6666 1 c4 1000pf multilayer cap, 16v, 10% generic h1045-00102-16v10 sm0603 8 c40, c41, c54-c56, c59-c61 10f multilayer cap, 6.3v, 20% murata panasonic tdk grm21br61c106ke15l ecj2fb0j106k c2012x5r0j106k sm0805 1 c6 15pf multilayer cap, 16v, 10% generic h1045-00150-16v10 sm0603 1 c82 0.056f multilayer cap, 16v, 10% generic h1045-00563-16v10 sm0603 0c81, c83 dnp 1 l1 0.88h inductor, inductance 20%, dcr 7% nec-tokin mpc1040lr88 10mmx10mm 1 q2 n-channel power mosfet ir irf7821 pwrpakso8 2q3, q9 n-channel power mosfet ir irf7832 pwrpakso8 1 r10 2.37k thick film chip resistor, 1% generic h2511-02371-1/16w1 sm0603 1 r11 6.98k thick film chip resistor, 1% generic h2511-06981-1/16w1 sm0603 1 r16 47.5k thick film chip resistor, 1% generic h2511-04752-1/16w1 sm0603 2 r17, r18 10 thick film chip resistor, 1% generic h2511-00100-1/16w1 sm0603 1 r19 1.91k thick film chip resistor, 1% generic h2511-01911-1/16w1 sm0603 1 r26 82.5 thick film chip resistor, 1% generic h2511-082r5-1/16w1 sm0603 3 r20, r40, r56 0 thick film chip resistor, 1% generic h2511-00r00-1/16w1 sm0603 1 r30 3.01k thick film chip resistor, 1% generic h2511-03011-1/16w1 sm0603 1 r37 1 thick film chip resistor, 1% generic h2511-01r00-1/16w1 sm0603 1 r38 11k thick film chip resistor, 1% generic h2511-01102-1/16w1 sm0603 1 r41 2.61k thick film chip resistor, 1% generic h2511-02611-1/16w1 sm0603 1 r42 10k ntc thermistor, 10k ntc panasonic ert-j1vr103j sm0603 1 r50 22.6k thick film chip resistor, 1% generic h2511-02262-1/16w1 sm0603
isl62882, isl62882b 33 fn6890.4 june 21, 2011 1 r6 10k thick film chip resistor, 1% generic h2511-01002-1/16w1 sm0603 1 r63 3.65k thick film chip resistor, 1% generic h2511-03651-1/16w1 sm0805 1 r7 412k thick film chip resistor, 1% generic h2511-04123-1/16w1 sm0603 0 r109, r110, r4, r8, r9 dnp 1 u6 imvp-6.5 pwm controller intersil ISL62882HRTZ qfn-40 1-phase gpu application referenc e design bill of materials (continued) qty reference value description manufacturer part number package 2-phase cpu application refere nce design bill of materials qty reference value description manufacturer part number package 1 c11 390pf multilayer cap, 16v, 10% generic h1045-00391-16v10 sm0603 1 c12 330pf multilayer cap, 16v, 10% generic h1045-00331-16v10 sm0603 1 c13 1000pf multilayer cap, 16v, 10% generic h1045-00102-16v10 sm0603 2 c15, c21 0.01f multilayer cap, 16v, 10% generic h1045-00103-16v10 sm0603 2 c16,c22 1f multilayer cap, 16v, 20% generic h1045-00105-16v20 sm0603 1 c18 0.33f multilayer cap, 16v, 10% generic h1045-00334-16v10 sm0603 1 c20 0.1f multilayer cap, 16v, 10% generic h1045-00104-16v10 sm0603 5 c9, c10, c17, c30, c31 0.22f multilayer cap, 25v, 10% generic h1045-00224-25v10 sm0603 2 c24,c25 56f radial sp series cap, 25v, 20% sanyo 25sp56m case-cc 4 c27,c28,c33,c34 10f multilayer cap, 25v, 20% generic h1065-00106-25v20 sm1206 1 c3 150pf multilayer cap, 16v, 10% generic h1045-00151-16v10 sm0603 3 c39, c52, c57 470f spcap, 2v, 4m polymer cap, 2.5v, 4.5m panasonic kemet eexsx0d471e4 t520v477m2r5a(1)e4r5-6666 1 c4 1000pf multilayer cap, 16v, 10% generic h1045-00102-16v10 sm0603 30 c40-c43, c47-c50, c53-c56, c59-c75, c78 10f multilayer cap, 6.3v, 20% murata panasonic tdk grm21br61c106ke15l ecj2fb0j106k c2012x5r0j106k sm0805 1 c5 22pf multilayer cap, 16v, 10% generic h1045-00220-16v10 sm0603 1 c6 10pf multilayer cap, 16v, 10% generic h1045-00100-16v10 sm0603 1 c81 1200pf multilayer cap, 16v, 10% generic h1045-00122-16v10 sm0603 1 c82 0.047f multilayer cap, 16v, 10% generic h1045-00473-16v10 sm0603 1 c83 560pf multilayer cap, 16v, 10% generic h1045-00561-16v10 sm0603 2 l1, l2 0.36h inductor, inductance 20%, dcr 7% nec-tokin panasonic mpch1040lr36 etqp4lr36afc 10mmx10mm 4 q2, q4, q8, q10 n-channel power mosfet ir irf7821 pwrpakso8 4 q3, q5, q9, q11 n-channel power mosfet ir irf7832 pwrpakso8 1 r10 562 thick film chip resist or, 1% generic h2511-05620-1/16w1 sm0603 1 r109 100 thick film chip resistor , 1% generic h2511-01000-1/16w1 sm0603 1 r11 2.87k thick film chip resistor , 1% generic h2511-02871-1/16w1 sm0603 1 r110 2.87k thick film chip resistor , 1% generic h2511-02871-1/16w1 sm0603 1 r12 499 thick film chip resist or, 1% generic h2511-04990-1/16w1 sm0603 1 r16 147k thick film chip resistor , 1% generic h2511-01473-1/16w1 sm0603
isl62882, isl62882b 34 fn6890.4 june 21, 2011 2 r17, r18 10 thick film chip resist or, 1% generic h2511-00100-1/16w1 sm0603 3 r19, r71, r72 10k thick film chip re sistor, 1% generic h2511-01002-1/16w1 sm0603 1 r23 1.91k thick film chip resistor, 1% generic h2511-01911-1/16w1 sm0603 1 r26 82.5 thick film chip resistor , 1% generic h2511-082r5-1/16w1 sm0603 4 r20, r40, r56, r57 0 thick film chip resistor, 1% generic h2511-00r00-1/16w1 sm0603 1 r30 1k thick film chip resistor, 1% generic h2511-01001-1/16w1 sm0603 3 r37, r88, r90 1 thick film chip resi stor, 1% generic h2511-01r00-1/16w1 sm0603 1 r38 11k thick film chip resistor , 1% generic h2511-01102-1/16w1 sm0603 1r4 dnp 1 r41 2.61k thick film chip resistor , 1% generic h2511-02611-1/16w1 sm0603 1 r42 10k ntc thermistor, 10k ntc panasonic ert-j1vr103j sm0603 1 r50 9.31k thick film chip resistor, 1% generic h2511-09311-1/16w1 sm0603 1 r6 8.06k thick film chip resistor , 1% generic h2511-08061-1/16w1 sm0603 2 r63, r65 3.65k thick film chip resi stor, 1% generic h2511-03651-1/16w1 sm0805 2 r8, r9 dnp 1 r7 412k thick film chip resistor , 1% generic h2511-04123-1/16w1 sm0603 1 u6 imvp-6.5 pwm controller intersil ISL62882HRTZ qfn-40 2-phase cpu application refere nce design bill of materials (continued) qty reference value description manufacturer part number package
isl62882, isl62882b 35 fn6890.4 june 21, 2011 typical performance figure 32. 2-phase ccm efficiency, vid = 1.075v, v in1 =8v, v in2 = 12.6v and v in3 = 19v figure 33. 2-phase ccm load line, vid = 1.075v, v in1 =8v, v in2 = 12.6v and v in3 = 19v figure 34. 1-phase dem efficiency, vid = 0.875v, dprslpvr is asserted for i out <3a, v in1 =8v, v in2 = 12.6v and v in3 = 19v. solid lines: isl62882 efficiency, dotted lines: would-be efficiency if lgate1b was not turned off in dprslpvr mode figure 35. 1-phase dem load line, vid = 0.875v, dprslpvr is asserted for i out <3a v in1 =8v, v in2 = 12.6v and v in3 = 19v figure 36. 2-phase cpu mode soft-start, v in =19v, i o = 0a, vid = 0.95v, ch1: phase1, ch2: v o , ch3: phase2 figure 37. 2-phase cpu modeshut down, v in = 19v, i o = 1a, vid = 0.95v, ch1: phase1, ch2: v o , ch3: phase2 70 72 74 76 78 80 82 84 86 88 90 92 0 5 10 15 20 25 30 35 40 45 50 55 i out (a) efficiency (%) v in = 8v v in = 19v vin = 12v 0.92 0.94 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 0 5 10 15 20 25 30 35 40 45 50 55 60 65 i out (a) v out (v) 55 60 65 70 75 80 85 90 0.1110100 i out (a) efficiency (%) v in = 19v v in = 12v v in = 8v v in = 8v 0.825 0.835 0.845 0.855 0.865 0.875 0.885 0 101112131415 i out (a) v out (v) 123456789
isl62882, isl62882b 36 fn6890.4 june 21, 2011 figure 38. 2-phase cpu mode clk_en# delay, v in = 19v, i o = 2a, vid = 1.5v, ch1: phase1, ch2: v o , ch4: clk_en# figure 39. 2-phase cpu mode pre-charged start up, v in = 19v, vid = 0.95v, ch1: phase1, ch2: v o , ch4: vr_on figure 40. steady state, v in = 19v, i o =0a, vid=1.075v, ch1: phase1, ch2: v o , ch3: phase2 figure 41. steady state, v in = 19v, i o = 35a, vid = 1.075v, ch1: phase1, ch2: v o , ch3: phase2 figure 42. load transient response with overshoot reduction function disabled, v in = 19v, vid = 1.075v, i o = 15a/50a, di/dt = ?fastest? figure 43. load transient response with overshoot reduction function disabled, v in = 19v, vid = 1.075v, i o = 15a/50a, di/dt = ?fastest? typical performance (continued)
isl62882, isl62882b 37 fn6890.4 june 21, 2011 figure 44. load transient response with overshoot reduction function disabled, v in = 19v, vid = 1.075v, i o = 15a/50a, di/dt = ?fastest? figure 45. load transient response with overshoot reduction function disabled, v in = 19v, vid = 1.075v, i o = 15a/50a, di/dt = ?fastest? figure 46. 2-phase cpu mode deeper sleep mode entry/exit, i o = 1.5a, hfm vid = 1.075v, lfm vid = 0.875v, deeper sleep vid = 0.875v, ch1: phase1, ch2: v o , ch3: phase2, ch4: dprslpvr figure 47. 2-phase cpu mode vid on the fly, 1.075v/0.875v, 2-phase configuration, psi# = 1, dprslpvr = 0, ch1: phase1, ch2: v o , ch3: phase2 figure 48. phase adding (psi# toggle), i o =15a, vid = 1.075v, ch1: phase1, ch2: v o , ch3: phase2, ch4: n/a figure 49. phase dropping (psi# toggle), i o =15a, vid = 1.075v, ch1: phase1, ch2: v o , ch3: phase2, ch4: n/a typical performance (continued)
isl62882, isl62882b 38 fn6890.4 june 21, 2011 figure 50. transient response with overshoot reduction function enabled, v in = 19v, vid = 0.95v, i o = 12a/51a, di/dt = ?fastest?, ch1: phase1, ch2: v o , ch3: n/a, ch4: lgate1 figure 51. 2-phase cpu mode reference design loop gain t2(s) measurement result figure 52. imon, vid = 1.075 figure 53. reference design fdim result figure 54. 1-phase gpu mode soft-start, dprslpvr=0, v in =8v, i o = 0a, vid = 1.2375v, ch1: phase1, ch2: v o figure 55. 1-phase gpu mode shut down, v in =8v, i o =1a, vid = 1.2375v, ch1: phase1, ch2: v o typical performance (continued) gain phase margin 0 100 200 300 400 500 600 700 800 900 1000 0 5 10 15 20 25 30 35 40 45 50 i out (a) i mon-vsssense (mv) v in = 8v v in = 19v v in = 12v spec 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 frequency (hz) 1k 10k 100k 1m z(f) (m ) psi# = 0, dprslpvr = 0, 1-phase de psi# = 1, dprslpvr = 0, 2-phase ccm
isl62882, isl62882b 39 fn6890.4 june 21, 2011 figure 56. 1-phase gpu mode vid transition, dprslpvr = 0, i o = 2a, vid = 1.2375v/1.0375v, ch2: v o , ch3: vid4 figure 57. 1-phase gpu mode vid transition, dprslpvr = 1, i o = 2a, vid = 1.2375v/1.0375v, ch2: v o , ch3: vid4 typical performance (continued)
isl62882, isl62882b 40 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6890.4 june 21, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog signal processi ng functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: isl62882 , isl62882b to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 5/6/11 fn6890.4 updated to most current intersil template. page 8, electrical spec table: added min and max limits for imon output current, condition isum ? pin current = 5a, min: 22 max: 37.5 page 8, note 6: updated over temp note in min max column of spec tables from "compliance to datasheet limits is assured by one or more methods: production test, char acterization and/or design." to: "param eters with min and/or max limits are 100% tested at +25c, unless otherwise specifie d. temperature limits established by charac terization and are not production tested." 2/10/11 fn6890.3 page 7, electrical spec table: removed min and max limits for imon output current, condition isum ? pin current = 5a pg 2 - updated tape & reel note in ordering information from "a dd ?-t? suffix for tape and reel." to new standard "add ?-t*? su ffix for tape and reel." the "*" covers all possible tape and reel options. removed -t fgs that are covered by "-t*" note (irtz-t, hrtz-t, bhrtz-t) updated intersil trademark statement at bott om of page 1 per directive from legal. updated over temp note in min max column of spec tables fr om "parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperat ure limits established by characterization and are not production tested." to new standard "compliance to datashee t limits is assured by one or more methods: prod uction test, characterization and/or design." electrical spec table: removed note 7 "limits established by ch aracterization and are not production tested." and references to it in the table. updated l40.5x5 pod to rev .1. changes from rev 0: added note 7 (jedec reference drawing: mo-220whhe-1) added note 4 callout to dimension b in bottom view 12/3/09 fn6890.2 removed isl62882a device from data sheet. 11/4/09 fn6890.2 converted to new intersil template. on page 19, mo des of operation section last pa ragraph changed from "rbias = 147kohm enables the overshoot reduction function and rbias = 47kohm disables it" to "rbias = 147kohm disables the overshoot reduction function and rbias = 47kohm enables it". applied intersil standards as follows: ordering information with notes and links, added bold verbiage to electrical sp ec conditions for over-temp and bolded min and max value columns. pin descriptions placed in table. 8/24/09 fn6890.1 8/18/09 - see attached .doc file for changes. 7/10/09: updated figures 1, 2, 10, 11 and 27. per jia, ?all the drawings have updated the way isen capacitors are connected. they used to be connected to from isen to gnd, now they are connected from isen to vo. it?s an application patch that helps to avoid false ibal fault during phase dropping due to an ic design error.? changed ?gnd? to ?vsum-? for pins 10 and 11 in table 5. pin 10 now reads ?a capacitor (c9) decouples it to vsum-. place it in general proximity of the controller.? pin 11 now reads ?a capacitor (c10) decouples it to vsum-. place it in general proximity of the controller.? 5/19/09: changed under recommended operat ing conditions- battery voltage vin from "+5v to 21v" to "+5v to 25v" 04/01/09 fn6890.0 initial release to web
isl62882, isl62882b 41 fn6890.4 june 21, 2011 package outline drawing l40.5x5 40 lead thin quad flat no-lead plastic package rev 1, 9/10 typical recommended land pattern detail "x" top view bottom view side view located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.27mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: (40x 0.60) 0.00 min 0.05 max (4x) 0.15 index area pin 1 pin #1 index area c seating plane base plane 0.08 see detail ?x? c c 5 6 a b b 0.10 m a c c 0.10 // 5.00 5.00 3.50 5.00 0.40 4x 3.60 36x 0.40 3.50 0.20 40x 0.4 0 .1 0.750 0.050 0.2 ref (40x 0.20) (36x 0.40 b package outline jedec reference drawing: mo-220whhe-1 7. 6 4
isl62882, isl62882b 42 fn6890.4 june 21, 2011 package outline drawing l48.6x6 48 lead thin quad flat no-lead plastic package rev 1, 4/07 typical recommended land pattern detail "x" side view top view bottom view located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 6.00 a b pin 1 index area (4x) 0.15 6 6.00 4.4 37 44x 0.40 4x pin #1 index area 48 6 4 .40 0.15 1 ab 48x 0.45 0.10 24 13 48x 0.20 4 0.10 c m 36 25 12 max 0.80 seating plane base plane 5 c 0 . 2 ref 0 . 00 min. 0 . 05 max. 0.10 c 0.08 c c see detail "x" ( 5. 75 typ ) ( 4. 40 ) ( 48x 0 . 20 ) ( 48x 0 . 65 ) ( 44 x 0 . 40 ) 0.05 m c

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